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RISC-V Summit North America 2022
Channel:
RISC-V International
Videos (97)
1 — Tutorial: Toolchains - Christoph Müllner, VRULL
2 — The OpenTitan Project - Dom Rizzo, Google
3 — Keynote: Accelerating Innovation with RISC-V: Past, Present and Future - Manju Varma
4 — RISC-V Spotlight: Improving RISC-V Quality with Verification Standards and Advanc... Simon Davidmann
5 — Keynote: RISC-V Challenges & Opportunities - Lip-Bu Tan
6 — Keynote: State of the Union - Krste Asanović, Professor, UC Berkeley & Chair of RISC-V International
7 — Keynote: The Android Open Source Project and RISC-V - Lars Bergstrom, Google Director of Engineering
8 — Keynote: HPSC – Radically Advancing the Capabilities of Space-based Computing - Pete Fiacco
9 — Is RISC-V HPC? RISC-V is HPC! - John Davis, Barcelona Supercomputing Center
10 — Keynote: Awards Presentation
11 — RISC-V FutureWatch - Ventana: Balaji Baktha, Founder and CEO, Ventana
12 — RISC-V FutureWatch - Microchip: RISC-V based Mid-range FPGAs: Fueling The Edge Comp... Shakeel Peera
13 — RISC-V FutureWatch - SiFive: Introducing the Horse Creek Development Board - Jack Kang, SVP, SiFive
14 — SERV: 32-bit is the New 8-bit - Olof Kindgren, Qamcom
15 — High-Performance RISC-V Processor for Computation Acceleration and Server - Wei-han Lien
16 — RISC-V FutureWatch: Introducing a New Software-defined Silicon Capability to the RIS... Mark Lippett
17 — Using RISC-V in Heterogeneous Solutions to Solve Compute Challenges Pres... Naresh Gangadharan Menon
18 — RISC-V FutureWatch: MIPS - Bringing a New Level of Scalability to RISC-V - MIPS eVoco... Itai Yaromm
19 — Democratizing Innovation in Automotive with RISC-V and Open Source - Gordan Markuš, Canonical Ltd.
20 — RISC-V Powered SoM Based Products and HPC Native Development - Yuning Liang, Xcalibyte
21 — Panel: Building a Scalable RISC-V Software Ecosystem
22 — Qualification of the C and C++ Standard Libraries for Safety-critical Applications - Remi van Veen
23 — RISC-V FutureWatch - Andes Technology: Expanding the RISC-V Horizon an... Frankwell Lin & Charlie Su
24 — A Linux Distribution’s View on RISC-V - Heinrich Schuchardt, Canonical
25 — Demo: RISC-V Cloud Lab - Ligang Zhang, Alibaba
26 — Future is Sideways - Not Only Up and Right - John Min, Andes Technology USA
27 — OS-A SEE Explained - Aaron Durbin, Rivos Inc.
28 — RISC-V Readiness for Datacenter Deployments - Balaji Baktha & Mark Himelstein
29 — RISC-V Spotlight: Avoiding Murphy's Law and Satan's Law Without Selling your Soul - Ron Black
30 — Demo: RISC-V Models for Verification, Software Development and Architectural Explor... Larry Lapides
31 — The Road Ahead - Mark Himelstein, RISC-V International
32 — Demo: Smart Embedded Vision with PolarFire® SoC FPGA - Krishnakumar (KK), Microchip
33 — StarFive's Efforts in Fuelling RISC-V Software Ecosystem - See Chin Liang, StarFive Technology
34 — RISC-V Spotlight: RISC-V: Everyone Wins - Patrick Little, Chairman, SiFive
35 — RISC-V Profiles and Profile Roadmap - Krste Asanovic, Chair, RISC-V International
36 — Empower Upstream ML Frameworks on RISC-V - Tiejun Chen, VMware
37 — Panel: It Takes a Village… to Bu... Amber Huffman, Dan Mender, Peter Lewin, Rob Aitken, Phil Dworsky
38 — RISC-V Spotlight: Ventana Brings RISC-V to Data Center with Veyron V1 - Balaji Baktha, Ventana
39 — Progress in Porting Android onto RISC-V: Testing, Performance and Open Source - Mao Han, Alibaba
40 — IoT True Wireless Stereo Applications Shine with RISC-V and HiFi DSP - Casey Ng, Cadence
41 — Demo: RISC-V Dual Lock-step Implementation for Safety and Security Applications - Paul Elliott
42 — Demo: Facilitating Trusted Application Migration to RISC-V - Xiaoxia Cui, Alibaba
43 — SiFive Intelligence & VCIX - Krste Asanovic, SiFive
44 — Introducing the Highest Performance RISC-V Development B... Sam Grove & Nikhil Krishna Gopalakrishna
45 — The RISC-V Vector Cryptography Extensions - G. Richard Newell & Ken Dockser
46 — Real World Results using Thousands of RISC-V Cores for AI and Beyond - Dave Ditzel, Esperanto
47 — RISC-V Perf-Model: An Open Source Cycle Accurate Performance Mo... Knute Lingaard & Arup Chakraborty
48 — New DSP Extensions to the Embench Benchmark Suite - Ray Simar, Rice University
49 — Automatic Test Generation and Verification for RISC-V Vector Extension - Shenwei Hu & Xi Wang, RIOS
50 — Open Standard Software Acceleration for RISC-V - Alastair Murray & Pierre-Andre Saulais, Codeplay
51 — I/O Virtualization Use Cases and the RISC-V IOMMU Overview - Ved Shanbhogue, Rivos Inc.
52 — Ocelot: Open Source Vector Unit - Srikanth Arekapudi & Dongjie Xie, Tenstorrent
53 — KUtrace For RISC-V - Richard Sites
54 — RISC-V for Aerospace and Defense Applications - Tom Leahy, SiFive
55 — Tutorial: Running the Architectural Compatibility Tests on your Model: Th... Neel Gala & Pawan Kumar
56 — Tutorial: High Level Sail Overview - Bill McSpadden, RISC-V International
57 — Getting the Most out of the LLVM Auto Vectorizer for RISC-V Vectors (RVV) - Kolya Panchenko, SiFive
58 — Introducing RISC-V Confidential Computing for IoT Devices - Bicheng Yang & Dingji Lee
59 — Advance the Performance Analysis on RISC-V - Fei Wu & Jiangang Duan, Intel
60 — MiniFloat-NN: A RISC-V ISA Extension for Low-Precision NN Training - Luca Bertaccini, ETH Zürich
61 — Beating the Benchmarks: Co-evolving the ISA and Development Tools - Philipp Tomsich, VRULL GmbH
62 — Tutorial: Performance Tools - Knute Lingaard, SiFive & Arup Chakraborty, Ventana Microsystems
63 — HW-SW Co-development for RISC-V Based Secure ML Systems with the Sparro... Michael Gielda & Kai Yick
64 — SCAIE-V: A Scalable Open-source Interface for Flexible and Portable ISA Extensions - Andreas Koch
65 — RISC-V Zkt: Portable Timing Attack Resistance (via Dynamic Taint Analys... Markku-Juhani O. Saarinen
66 — Tutorial: Side-Channel Attacks and Transient Execution Vulnerab... Allison Randal & Giorgos Christou
67 — RISC-V Power and Performance Management - Andrew Jones & Sunil V L, Ventana Micro Systems Inc.
68 — RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues - Adnan Hamid, Breker Verification
69 — Confidential Computing for RISC-V-based Platforms - Ravi Sahita, Rivos Inc.
70 — Demo: Enhancing the SiFive Performance Portfolio - Drew Barbier, SiFive
71 — Demo: AI Solution Including AndesClarity and NN/Vector Libraries - Hubert Chung, Andes Technology
72 — Demo: Catapult Studio for the RTXM-2200 RISC-V CPU - Chris Owen, Imagination Technology
73 — Demo: CORE-V MCU with CV32E40P Processor Core - Dan Gross, AWS
74 — Tutorial: Choosing Appropriate Verification Techniques for Desired RISC... Aimee Sutton & Lee Moore
75 — Tutorial: Virtualization - Sandro Pinto, Universidade do Minho (Portugal)
76 — Demo: Introduction to RISC-V Verification with the Open Standard RVVI (RISC-V Verifi... Aimee Sutton
77 — Demo: Storage Acceleration with SPDK on RISC-V - Kumar Sankaran, Ventana Micro Systems
78 — RISC-V Spotlight: Expanding the RISC-V Horizon and Beyond - Charlie Su, President and CTO, Andes
79 — RISC-V Spotlight: Scrum for Success - Shreyas Derashri, VP of Compute, Imagination Technologies
80 — Introducing PathProfiler – A Hardware Mechanism to Profile Dynamic Execution - Bruce Ableidinger
81 — Update on Fast Interrupt Task Group (CLIC) Since Barcelona 2018 - Dan Smathers, Seagate Technology
82 — Building a Global CORE-V Cores Ecosystem - Mike Thompson, OpenHW Group
83 — The Continuum of RISC-V Compliance and Verification Testing - Simon Davidmann & Allen Baum
84 — RISC-V FutureWatch - Imperas: The 360 Ecosystem of RISC-V - Simon Davidmann, CEO at Imperas Software
85 — Proving RISC-V Security Model Compliance with SESIP - Eve Atallah, NXP Semiconductors
86 — Demo: SmartNIC with OvS-DPDK on RISC-V - Kumar Sankaran, Ventana Micro Systems
87 — RISC-V Spotlight: How RISC-V Speeds the Journey of Innovation - Bruce Weyer, Microchip
88 — Redefining the Embedded Development Landscape with Software-defined SoCs - Mark Lippett, XMOS
89 — The New Verification Ecosystem that Supports RISC-V Verification fo... Lee Moore & John Sotiropoulos
90 — RISC-V Nested Virtualization - Anup Patel, Ventana Micro Systems Inc
91 — RISC-V and the Elf: A Story About Randomisation for Safe and Secure Critical Sy... Leonidas Kosmidis
92 — Adaptable, Scalable and Predictable Computing with a Multi-threaded RISC-V Architectu... Henk Muller
93 — Panel: RISC-V in Education and Training: Successes and Gaps
94 — Tutorial: Spike Usage and Adding A New RISC-V Extension Support to Spike - Eop Chen, SiFive
95 — Demo: Intel® Pathfinder for RISC-V Product Overview - Dalon Westergreen
96 — TII interview at RISC-V Summit North America 2022
97 — RISC-V Summit North America 2022 Highlights