RISC-V Summit Europe 2025 Day 3

Channel: RISC-V International

Videos (27)

1 — Open-Source Xiangshan Nanhu Processor Experience Day
2 — Developing Custom RISC-V ISA Extensions for General Embedded Image Processing Operations
3 — OmniXtend: Open Coherent Memory Fabric for RISC-V
4 — Spike-RTL: quasi-cycle accuracy hardware/software co-simulation
5 — MemPool Flavors: Between Versatility and Specialization in a RISC-V Manycore Cluster
6 — “One Student One Chip” - Learn to Create Your Own RISC-V Processor From Scratch
7 — METASAT Demonstrator: Mixed Criticality, Accelerated AI Computing for Future Space Systems
8 — FGMT-RiscV running on an FPGA evaluation board with a live GDB debug session
9 — Optimizing Sparse matrix-vector multiplication on the EPAC architecture
10 — Fast and fine-grained compartmentalisation in CHERI
11 — Open Source Chip Design in the European Semiconductor Strategy
12 — Improvements to RISC-V Vector code generation in LLVM
13 — Challenge Accepted: Python Packaging Infrastructure for the RISCV64 Ecosystem
14 — Unleashing the Power of RISC-V E-Trace with a Highly Efficient Software Decoder
15 — Compared Analysis of GCC Codegen for AArch64 and RISC-V
16 — Profiling Whisper AI Model on RISC-V: CPU, GPU, and NPU Performance on the DC-ROMA AI PC
17 — A RISC-V Compatible Systolic Array for TinyML Applications in CFU Playground
18 — Awards Ceremony
19 — The Significance of the RVA23 Profile in Advancing RISC-V Ecosystem
20 — Panel – Enterprise Linux Enablement on RISC-V
21 — RISC-V open designs and contributions to hardware security research and development activities
22 — OpenTitan Integrated: A RISC-V Open-Source Silicon Root-of-Trust for large SoCs
23 — Farewell and upcoming Summits
24 — Efficient debug and trace of RISC-V systems: a hardware/software co-design approach
25 — Going BIG With the RISC-V Ecosystem
26 — Towards Open-Source and Automatic Performance Characterization Hardware
27 — RISC-V: Reaching New Orbits in Space Computing