RISC-V Summit Europe 2024 - Demo Theater

Channel: RISC-V International

Videos (25)

1 — Driving SoC Innovation with Synopsys RISC-V Solutions - Rich Collins, Synopsys
2 — Enhancements to SiFive’s Essential product line - Pete Lewin, SiFive
3 — Accelerate RISC-V DSA design with Virtual Board Builder - Hualin Wu, Terapines Technology
4 — Introduction of XuanTie RISC-V - James Shi (Qinghao Shi), Alibaba Damo
5 — Exploring RISC-V architectures with VPSim, a virtual prototyping environment - Lilia Zaourar, CEA
6 — AI custom Software/Hardware Interface improving performance 5-10x - Keith Graham, Codasip
7 — Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips - M. Schleinkofer, Lauterbach
8 — KVM device assignment for virtual machines using the RISC-V IOMMU - Andrew Jones, Ventana
9 — Introducing Sonata — the new open source platform for CHERIoT development - Greg Chadwick, lowRISC
10 — Scale4Edge RISC-V Ecosystem - Andreas Mauderer, Bosch
11 — CHERI in out-of-order microarchitecturesFranz Fuchs, University of Cambridge
12 — TETRISC SoC, an fault-tolerant and adaptive quad-core system - Junchao Chen, IHP Microelectronics
13 — RISC-V enabled, low-power CNN classification in Edge devices - Per Andersson, Lund University
14 — Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions - P Marcuello, Semidynamics
15 — Breaking the RISC-V Processor Customization Barrier with Formal Verification - Sven Beyer, Siemens
16 — Andes High Value RISC-V Processors and Their Application - Frankwell Lin, Andes
17 — ESWIN EIC7700X/7702X, Pioneer of RISC-V Computing Solution - Bo Wang, Beijing ESWIN Computing
18 — UnityChip Verification: Open-Source RISC-V Verification at BOSC - Shan Liu, BOSC
19 — The NOEL Processor LineJan Andersson Nerén, Frontgrade Gaisler
20 — Hackathon Presentations
21 — The European Accelerator (EPAC) demonstrator with 3 RISC-V based accelerators - F. Mantovanni, BSC
22 — End-to-end flow to automatically generate and integrate RISC-V ISA extensions -Mürmann, TU Darmstadt
23 — RISC-V Instruction Set Explorer (RISE) - Lennart M. Reimann, RWTH Aachen
24 — Simulate, trace, and evaluate a RISC-V system leveraging very long vectors - Pablo Vizcaino, BSC
25 — The role of an Open Computing Architecture in EU Digital sovereignty - Luis Busquets, DG CONNECT