RISC-V Global Forum 2020 - virtual

Channel: RISC-V International

Videos (39)

1 — Portable Implementation of GlobalPlatform API for TEE - Kenta Nakajima & Kuniyasu Suzaki, TRASIO
2 — Vector Compliance Testing for RISC-V - Hideki Sugimoto & Koji Adachi, NSITEXE Inc.
3 — Nutshell: A Linux-Compatible RISC-V Processor Designed by Undergraduates - Huaqiang Wang
4 — Andes RISC-V Processors for Control and Data Paths - Charlie Su, Andes Technology Corporation
5 — TEEP (Trusted Execution Environment Provisioning) on RISC-V - Akira Tsukamoto & Kuniyasu Suzaki
6 — PicoRio: An Open-Source, RISC-V Small-Board Computer To Elevate The RISC-V Software... - Zhangxi Tan
7 — Support TVM QNN Flow on RISC-V with SIMD Computation - Yi-Ru Chen & Jenq Kuen Lee
8 — CloudBEAR RISC-V Processor IP Product Line - Alexander Kozlov, CloudBEAR
9 — Optimize Openblas by RISC-V "V" Vector Extension - Xianyi Zhang, PerfXLab
10 — Software Development for 64-Bit RISC-V Processor Verification - Sreenadh S & Sangeetha N.
11 — An Introduction to RISC-V Vector Programming with C Intrinsics - Chih-Mao Chen, Andes Technology
12 — BM-310 Small and Efficient MCU Core - Alexander Kozlov, CloudBEAR
13 — ProtoCPU: Modelling an In-Order RISC-V Core in gem5 - Anuj Justus Rajappa, IIT Madras
14 — Optimizing RISC-V Custom Instructions with Software Driven Anal... - Duncan Graham & Simon Davidmann
15 — Keynote: Information Revolution, Chips, and Openness - Shahin Khan, Founding Partner, OrionX.net
16 — Keynote: RISC-V - A User's Perspective - Loic Lietar, GreenWaves
17 — CORE-V Verification Test Bench – Commercial Qualit... - Rick O'Connor; Simon Davidmann; Aimee Sutton
18 — Keynote: Closing Remarks - Calista Redmond, CEO, RISC-V International
19 — Keynote: EPI, The European Approach for Exascale Ages. The Road Toward Sovereignty - Jean-Marc Denis
20 — Keynote: The Open Source Hardware Roadmap - Zvonimir Bandic, Chairman, CHIPS Alliance
21 — The Case for RISC-V in Space - Gianluca Furano, European Space Agency
22 — Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs - Dr. Ashish Darbari, AXIOMISE
23 — RISC-V True Random Number Generation: Probably Too Important to be Le... - Markku-Juhani O. Saarinen
24 — Omnixtend Boot Protocol and Coherent Scaleout - Dejan Vucinic, Western Digital Corporation
25 — Keynote: RISC-V in Academia and Education - Stefan Wallentowitz & Calista Redmond
26 — Code Size Compiler Optimizations and Techniques for Embedded Systems - Aditya Kumar, Facebook
27 — Where Is the 32-Bit Glibc Port? - Alistair Francis, Western Digital
28 — Unlocking Javascript: V8 on RISC-V - Peng Wu & Brice Dobry, Futurewei Technologies
29 — An Automated Scalable RISC-V Cache Coherency Verification Project - Adnan Hamid, Breker Verification
30 — Stay Ahead with the Latest Advances in RISC-V Development Tools - Shawn Prestridge, IAR Systems
31 — Verifying All the Flexibility of RISC-V within SoC DV Test Plans - Simon Davidmann & Lee Moore
32 — RVfpga: Using A Commercial RISC-V Processor to Teac... - Sarah L. Harris & Daniel A. Chaver Martinez
33 — Noel-V: A New High-Performance RISC-V Processor Family - Johan Klockars & Alen Bardizbanyan
34 — Riscof - A Risc-V Compliance Framework and More - Neel Gala, InCore Semiconductors
35 — Keynote: NVIDIA’s secure RISC-V processor - Frans Sijstermans & Joe Xie, NVIDIA
36 — Semidynamics New Family of High Bandwidth Vector-Capable Cores - Roger Espasa, SemiDynamics
37 — Trusted Execution State: An Extension for Lightweight Secure Function Calling - Mark Hill, Huawei
38 — Keynote: An Investor Perspective on RISC-V, The Opportunities and Challenges Ahead - Guru Chahal
39 — Cloud-based Verification of Open Source RISC-V Cores Using the Metr... Roddy Urquhart & Dan Ganousis