Day 3 Keynotes & Technical Sessions | RISC-V Summit Europe 2023

Channel: RISC-V International

Videos (18)

1 — Philipp Tomsich, VRULL GmbH - SW-driven evolution of a uniquely modular and extensible ISA
2 — Thierry Collette, Thales R&T - 4 years of Open Source RISC-V at Thales
3 — Wei-han Lien, Tenstorrent - A High-Fidelity Flow for High-Performance RISC-V CPU Design from Scratch
4 — David Mallasén Quintana - PERCIVAL: Integrating Posit and Quire Arithmetic into the RISC-V Ecosystem
5 — Alex Bradbury, Igalia - Developments in LLVM-based toolchains and tooling for RISC-V
6 — Andrei Warkentin - Multi-ISA Firmware Compatibility - Bringing RISC-V and IHV Ecosystems Together
7 — Stanislaw Kaushanski - Automated Cross-level Verification Flow of a Highly Configurable RISC-V Core
8 — Tariq Kurd-RISC-V code-size reduction w/ Zc extensions and dictionary compression custom instruction
9 — Roland Weigand - RISC-V: a Rising Star in Space
10 — Luca Lingardo-Implementation of an Edge-Computing architecture based on a RISC-V core for RFID Comms
11 — Guy Lemieux - From CCX to CIX: A Modest Proposal for (Custom) Composable Instruction eXtensions
12 — Andrei Ivanov- RIVETS: An Efficient Training and Inference Library for RISC-V with Snitch Extensions
13 — Gregory Chadwick - Building commercially relevant open source silicon: The many aspects of Ibex
14 — Thomas Benz, ETH Zürich - Puma: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS
15 — Bruno Sá, University Of Minho - RISC-V Virtualization: A Case Study on the CVA6
16 — Marton Bognar - Proteus: An Extensible RISC-V Core for Hardware Extensions
17 — Yifei Zhu|GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations
18 — Calista Redmond, RISC-V International & Christian Fabre, CEA & more - Closing & Announcements